Commit ebe3f5f6 authored by Maciej Sumiński's avatar Maciej Sumiński Committed by Javier D. Garcia Lasheras

Output include_dirs variable for Icarus simulation (NOTE: patch rebased by project manager)

parent 2ece8425
...@@ -64,8 +64,6 @@ class ToolControls(MakefileWriter): ...@@ -64,8 +64,6 @@ class ToolControls(MakefileWriter):
def generate_simulation_makefile(self, fileset, top_module): def generate_simulation_makefile(self, fileset, top_module):
# TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial VHDL support # TODO FLAGS: 2009 enables SystemVerilog (ongoing support) and partial VHDL support
# TODO: include dir
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module} makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
...@@ -86,6 +84,9 @@ simulation: ...@@ -86,6 +84,9 @@ simulation:
self.writeln("\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command") self.writeln("\t\techo \"# IVerilog command file, generated by HDLMake\" > run.command")
for inc in top_module.include_dirs:
self.writeln("\t\techo \"+incdir+" + inc + "\" >> run.command")
for vl in fileset.filter(VerilogFile): for vl in fileset.filter(VerilogFile):
self.writeln("\t\techo \"" + vl.rel_path() + "\" >> run.command") self.writeln("\t\techo \"" + vl.rel_path() + "\" >> run.command")
......
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