srcfile.py 8.03 KB
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# -*- coding: utf-8 -*-
#
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# Copyright (c) 2013, 2014 CERN
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# Author: Pawel Szostek (pawel.szostek@cern.ch)
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# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
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#
# This file is part of Hdlmake.
#
# Hdlmake is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# Hdlmake is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with Hdlmake.  If not, see <http://www.gnu.org/licenses/>.
#
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from __future__ import print_function
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#from dependable_file import DependableFile
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import os
import global_mod
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import logging
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from module import Module
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from util import path as path_mod
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from dep_file import DepFile, File
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class SourceFile(DepFile):
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    cur_index = 0
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    def __init__(self, path, module, library=None):
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        from dep_file import DepFile
        assert isinstance(path, basestring)
        assert isinstance(module, Module)
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        self.library = library
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        if not library:
            self.library = "work"
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        DepFile.__init__(self,
                         file_path=path,
                         module=module,
                         include_paths=module.include_dirs[:])

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    def __hash__(self):
        return hash(self.path + self.library)

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class VHDLFile(SourceFile):
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    def __init__(self, path, module, library=None, vcom_opt=None):
        SourceFile.__init__(self, path=path, module=module, library=library)
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        if not vcom_opt:
            self.vcom_opt = ""
        else:
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            self.vcom_opt = vcom_opt
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    def _check_encryption(self):
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        f = open(self.path, "rb")
        s = f.read(3)
        f.close()
        if(s == b'Xlx'):
            return True
        else:
            return False

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class VerilogFile(SourceFile):
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    def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
        SourceFile.__init__(self, path=path, module=module, library=library)
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        if not vlog_opt:
            self.vlog_opt = ""
        else:
            self.vlog_opt = vlog_opt
        self.include_dirs = []
        if include_dirs:
            self.include_dirs.extend(include_dirs)
        self.include_dirs.append(path_mod.relpath(self.dirname))

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class SVFile(VerilogFile):
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    pass
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class UCFFile(File):
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    pass
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class TCLFile(File):
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    pass
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class XISEFile(File):
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    pass
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class CDCFile(File):
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    pass
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class SignalTapFile(File):
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    pass
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class SDCFile(File):
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    # Synopsys Design Constraints
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    pass
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class QIPFile(File):
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    pass
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class DPFFile(File):
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    pass
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class XMPFile(File):
    # Xilinx Embedded Micro Processor
    pass

class PPRFile(File):
    # Xilinx PlanAhead Project
    pass

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class XPRFile(File):
    # Xilinx Vivado Project
    pass

class BDFile(File):
    # Xilinx Block Design
    pass

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class XCOFile(File):
    # Xilinx Core Generator File
    pass

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# class NGCFile(SourceFile):
#     def __init__(self, path, module):
#         SourceFile.__init__(self, path=path, module=module)
class NGCFile(File):
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    # Xilinx Generated Netlist File
    pass

class LDFFile(File):
    # Lattice Diamond Project File
    pass

class LPFFile(File):
    # Lattice Preference/Constraint File
    pass

class EDFFile(File):
    # EDIF Netlist Files
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    pass
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class PDCFile(File):
    # Physical Design Constraints
    pass
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class WBGenFile(File):
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    pass
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class SourceFileSet(set):
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    def __init__(self):
        super(SourceFileSet, self).__init__()
        self = []

    def __str__(self):
        return str([str(f) for f in self])

    def add(self, files):
        if isinstance(files, str):
            raise RuntimeError("Expected object, not a string")
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        elif files is None:
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            logging.debug("Got None as a file.\n Ommiting")
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        else:
            try:
                for f in files:
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                    super(SourceFileSet, self).add(f)
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            except:  # single file, not a list
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                super(SourceFileSet, self).add(files)
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    def filter(self, type):
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        out = SourceFileSet()
        for f in self:
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            if isinstance(f, type):
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                out.add(f)
        return out
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    def inversed_filter(self, type):
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        out = SourceFileSet()
        for f in self:
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            if not isinstance(f, type):
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                out.add(f)
        return out

    def get_libs(self):
        ret = set()
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        for file in self:
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            try:
                ret.add(file.library)
            except:
                pass
        return ret
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class SourceFileFactory:
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    def new(self, path, module, library=None, vcom_opt=None, vlog_opt=None, include_dirs=None):
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        if path == "/home/pawel/cern/wr-cores/testbench/top_level/gn4124_bfm.svh":
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            raise Exception()
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        if path is None or path == "":
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            raise RuntimeError("Expected a file path, got: "+str(path))
        if not os.path.isabs(path):
            path = os.path.abspath(path)
        tmp = path.rsplit('.')
        extension = tmp[len(tmp)-1]
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        logging.debug("add file " + path)
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        nf = None
        if extension == 'vhd' or extension == 'vhdl' or extension == 'vho':
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            nf = VHDLFile(path=path,
                          module=module,
                          library=library,
                          vcom_opt=vcom_opt)
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        elif extension == 'v' or extension == 'vh' or extension == 'vo' or extension == 'vm':
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            nf = VerilogFile(path=path,
                             module=module,
                             library=library,
                             vlog_opt=vlog_opt,
                             include_dirs=include_dirs)
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        elif extension == 'sv' or extension == 'svh':
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            nf = SVFile(path=path,
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                        module=module,
                        library=library,
                        vlog_opt=vlog_opt,
                        include_dirs=include_dirs)
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        elif extension == 'ngc':
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            nf = NGCFile(path=path, module=module)
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        elif extension == 'ucf':
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            nf = UCFFile(path=path, module=module)
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        elif extension == 'cdc':
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            nf = CDCFile(path=path, module=module)
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        elif extension == 'wb':
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            nf = WBGenFile(path=path, module=module)
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        elif extension == 'tcl':
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            nf = TCLFile(path=path, module=module)
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        elif extension == 'xise' or extension == 'ise':
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            nf = XISEFile(path=path, module=module)
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        elif extension == 'stp':
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            nf = SignalTapFile(path=path, module=module)
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        elif extension == 'sdc':
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            nf = SDCFile(path=path, module=module)
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        elif extension == 'qip':
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            nf = QIPFile(path=path, module=module)
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        elif extension == 'dpf':
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            nf = DPFFile(path=path, module=module)
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        elif extension == 'xmp':
            nf = XMPFile(path=path, module=module)
        elif extension == 'ppr':
            nf = PPRFile(path=path, module=module)
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        elif extension == 'xpr':
            nf = XPRFile(path=path, module=module)
        elif extension == 'bd':
            nf = BDFile(path=path, module=module)
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        elif extension == 'xco':
            nf = XCOFile(path=path, module=module)
        elif extension == 'ldf':
            nf = LDFFile(path=path, module=module)
        elif extension == 'lpf':
            nf = LPFFile(path=path, module=module)
        elif extension == 'edf' or extension == 'edif' or extension == 'edi' or extension == 'edn':
            nf = EDFFile(path=path, module=module)
        elif extension == 'pdc':
            nf = PDCFile(path=path, module=module)
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        return nf