Reorder simulation and external commands targets

parent 928c2c7b
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -56,7 +56,9 @@ run.command \
library.cfg
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
top_module=top_module.top_module
......@@ -86,7 +88,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -97,7 +99,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd *.asdb
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -61,7 +61,9 @@ GHDL_CRAP := \
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
......@@ -82,7 +84,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -93,7 +95,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Modified to allow ISim simulation by Lucas Russo (lucas.russo@lnls.br)
# Modified to allow ISim simulation by Adrian Byszuk (adrian.byszuk@lnls.br)
......@@ -86,14 +86,16 @@ ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini """ + self.__get_rid_of_isim_incdirs(top_module.vlog_opt) + """
"""
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
local: sim_pre_cmd simulation sim_post_cmd
simulation: xilinxsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ) fuse
$$(VERILOG_OBJ): $$(LIB_IND) xilinxsim.ini
$$(VHDL_OBJ): $$(LIB_IND) xilinxsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
xilinxsim.ini: $$(XILINX_INI_PATH)/xilinxsim.ini
......@@ -104,7 +106,7 @@ fuse:
clean:
\t\trm -rf ./xilinxsim.ini $$(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log \
isim.wdb isim_proj isim_proj.*
.PHONY: clean sim_pre_cmd sim_post_cmd
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
""")
#open the file and write the above preambule (part 1)
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -73,7 +73,9 @@ IVERILOG_CRAP := \
run.command
#target for performing local simulation
sim: sim_pre_cmd
local: sim_pre_cmd simulation sim_post_cmd
simulation:
""")
makefile_text_1 = makefile_tmplt_1.substitute(
......@@ -99,7 +101,7 @@ sim: sim_pre_cmd
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
#target for cleaning all intermediate stuff
......@@ -110,7 +112,7 @@ clean:
mrproper: clean
\t\trm -f *.vcd *.vvp
.PHONY: mrproper clean sim sim_pre_cmd sim_post_cmd
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
""")
if top_module.sim_pre_cmd:
......
#!/usr/bin/python
# -*- coding: utf-8 -*-
#
# Copyright (c) 2013, 2014 CERN
# Copyright (c) 2013 - 2015 CERN
# Author: Pawel Szostek (pawel.szostek@cern.ch)
# Multi-tool support by Javier D. Garcia-Lasheras (javier@garcialasheras.com)
#
......@@ -75,21 +75,24 @@ VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_vsim_incd
else:
make_preambule_p1 = make_preambule_p1.format(os.path.join("$(HDLMAKE_MODELSIM_PATH)", ".."))
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
local: sim_pre_cmd simulation sim_post_cmd
simulation: modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ) : modelsim.ini
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
\t\t${sim_pre_cmd}
sim_post_cmd: sim
sim_post_cmd:
\t\t${sim_post_cmd}
modelsim.ini: ${modelsim_ini_path}
\t\tcp $$< . 2>&1
clean:
\t\trm -rf ./modelsim.ini $$(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd
.PHONY: clean sim_pre_cmd sim_post_cmd simulation
""")
#open the file and write the above preambule (part 1)
......
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