Fixed issue with vcom, vmap and vsim options

parent d342f521
......@@ -64,7 +64,11 @@ class VsimMakefileWriter(MakefileWriter):
etc are defined by the specific tool.
"""
from srcfile import VerilogFile, VHDLFile, SVFile
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
self.vlog_flags.append(self.__get_rid_of_vsim_incdirs(top_module.vlog_opt))
self.vcom_flags.append(top_module.vcom_opt)
self.vmap_flags.append(top_module.vmap_opt)
self.vsim_flags.append(top_module.vsim_opt)
tmp = """## variables #############################
PWD := $(shell pwd)
......
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