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Commit b5324ddd authored by Adrian Fiergolski's avatar Adrian Fiergolski

Fix bug 1027.

parent c9306eea
......@@ -76,7 +76,7 @@ VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_vsim_incd
make_preambule_p1 = make_preambule_p1.format(os.path.join("$(HDLMAKE_MODELSIM_PATH)", ".."))
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ): $$(VHDL_OBJ)
$$(VERILOG_OBJ) : modelsim.ini
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
......
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