Commit c29256fc authored by jozsef imrek's avatar jozsef imrek Committed by Javier D. Garcia Lasheras

This commit closes #1276

parent 64f3ef14
......@@ -163,6 +163,10 @@ class PDCFile(File):
class WBGenFile(File):
pass
class QSFFile(File):
# Quartus Settings File
pass
class SourceFileSet(set):
def __init__(self):
......@@ -276,4 +280,6 @@ class SourceFileFactory:
nf = EDFFile(path=path, module=module)
elif extension == 'pdc':
nf = PDCFile(path=path, module=module)
elif extension == 'qsf':
nf = QSFFile(path=path, module=module)
return nf
......@@ -178,7 +178,7 @@ mrproper:
return pre+'\n'+mod+'\n'+post+'\n'
def __emit_files(self):
from hdlmake.srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile
from hdlmake.srcfile import VHDLFile, VerilogFile, SignalTapFile, SDCFile, QIPFile, DPFFile, QSFFile
tmp = "set_global_assignment -name {0} {1}"
tmplib = tmp + " -library {2}"
ret = []
......@@ -195,6 +195,8 @@ mrproper:
line = tmp.format("QIP_FILE", f.rel_path())
elif isinstance(f, DPFFile):
line = tmp.format("MISC_FILE", f.rel_path())
elif isinstance(f, QSFFile):
line = tmp.format("SOURCE_TCL_SCRIPT_FILE", f.rel_path())
else:
continue
ret.append(line)
......
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