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Simple 8-bit counter test for syn/sim, VHDL/Verilog

parent 1d66eb8b
//-----------------------------------------------------
// Design : Simple 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//-----------------------------------------------------
module counter (
clock,
clear,
count,
Q
);
//--------- Output Ports ------------------------------
output [7:0] Q;
//--------- Input Ports -------------------------------
input clock, clear, count;
//--------- Internal Variables ------------------------
reg [7:0] Q;
//--------- Code Starts Here --------------------------
always @(posedge clock)
if (clear) begin
Q <= 8'b0 ;
end else if (count) begin
Q <= Q + 1;
end
endmodule
-------------------------------------------------------
-- Design : Simple 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
-------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------
entity counter is
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end counter;
-------------------------------------------------------
architecture behv of counter is
signal Pre_Q: unsigned(7 downto 0);
begin
process(clock, count, clear)
begin
if clear = '1' then
Pre_Q <= "00000000";
elsif (clock='1' and clock'event) then
if count = '1' then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
Q <= std_logic_vector(Pre_Q);
end behv;
-------------------------------------------------------
asim +access +r counter_tb
trace -rec *
run 6 us
endsim
quit
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "aldec"
top_module = "counter_tb"
sim_post_cmd = "vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "ghdl"
top_module = "counter_tb"
sim_post_cmd = "ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
wave add /
vcd dumpfile counter_tb.vcd
vcd dumpvars -m counter_tb -l 1
run 6000 ns
#exit
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
target = "xilinx"
sim_tool = "isim"
top_module = "counter_tb"
sim_post_cmd = "./isim_proj -gui -tclbatch ../isim_cmd"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/verilog" ],
}
action = "simulation"
sim_tool = "modelsim"
top_module = "counter_tb"
sim_post_cmd = "vsim -do ../vsim.do -i counter_tb"
modules = {
"local" : [ "../../../testbench/counter_tb/vhdl" ],
}
vcd file counter_tb.vcd;
vcd add -r /*;
add wave *
run 6000ns;
view wave;
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/verilog" ],
}
target = "lattice"
action = "synthesis"
syn_device = "lfxp2-5e"
syn_grade = "-6"
syn_package = "tn144c"
syn_top = "brevia2_top"
syn_project = "demo"
syn_tool = "diamond"
modules = {
"local" : [ "../../../top/brevia2_dk/vhdl" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/verilog" ],
}
target = "altera"
action = "synthesis"
syn_device = "ep3c25"
syn_grade = "c6"
syn_package = "f324"
syn_top = "cyclone3_top"
syn_project = "demo"
syn_tool = "quartus"
quartus_preflow = "../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule = "../../../top/cyclone3_sk/module.tcl"
modules = {
"local" : [ "../../../top/cyclone3_sk/vhdl" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/verilog" ],
}
target = "microsemi"
action = "synthesis"
syn_device = "a3p250"
syn_grade = "-2"
syn_package = "208 pqfp"
syn_top = "proasic3_top"
syn_project = "demo"
syn_tool = "libero"
modules = {
"local" : [ "../../../top/proasic3_sk/vhdl" ],
}
......@@ -4,12 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "half2"
syn_project = "half2.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = [
"../../../modules/filtdec/half2.v",
"../../../modules/filtdec/reg_delay.v"
]
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
......@@ -4,9 +4,11 @@ action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "myfilter"
syn_project = "myfilter.xise"
syn_top = "spec_top"
syn_project = "demo.xise"
syn_tool = "ise"
files = ["../../../modules/fir/myfilter.vhd"]
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/verilog" ],
}
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "demo"
syn_tool = "planahead"
modules = {
"local" : [ "../../../top/spec_v4/vhdl" ],
}
files = [
"counter_tb.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Simple testbench for an 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, clear, count;
wire [7:0] Q;
// Initialize all variables
initial begin
$dumpfile("counter_tb.vcd");
$dumpvars(0,counter_tb);
$display ("time\t clock clear count Q");
$monitor ("%g\t %b %b %b %b",
$time, clock, clear, count, Q);
clock = 1; // initial value of clock
clear = 0; // initial value of clear
count = 0; // initial value of count enable
#5 clear = 1; // Assert the clear signal
#10 clear = 0; // De-assert clear signal
#10 count = 1; // Start count
#2000 count = 0; // De-assert count enable
#5 $finish; // Terminate simulation
end
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
counter U_counter (
clock,
clear,
count,
Q
);
endmodule
files = [
"counter_tb.vhd",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Simple testbench for an 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity counter_tb is -- entity declaration
end counter_tb;
-----------------------------------------------------------------------
architecture testbench of counter_tb is
component counter
port(
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal t_clock: std_logic;
signal t_clear: std_logic;
signal t_count: std_logic;
signal t_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter port map (t_clock, t_clear, t_count, t_Q);
process
begin
t_clock <= '0'; -- clock cycle is 10 ns
wait for 5 ns;
t_clock <= '1';
wait for 5 ns;
end process;
process
begin
t_clear <= '1'; -- start counting
t_count <= '1';
wait for 50 ns;
t_clear <= '0'; -- clear output
wait for 1000 ns;
report "Testbench of Adder completed successfully!"
severity note;
wait;
end process;
end testbench;
----------------------------------------------------------------
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "led_o_0" SITE "46" ;
LOCATE COMP "led_o_1" SITE "45" ;
LOCATE COMP "led_o_2" SITE "44" ;
LOCATE COMP "led_o_3" SITE "43" ;
LOCATE COMP "led_o_4" SITE "40" ;
LOCATE COMP "led_o_5" SITE "39" ;
LOCATE COMP "led_o_6" SITE "38" ;
LOCATE COMP "led_o_7" SITE "37" ;
LOCATE COMP "clear_i" SITE "50" ;
LOCATE COMP "count_i" SITE "53" ;
LOCATE COMP "clock_i" SITE "21" ;
LOCATE COMP "clken_o" SITE "22" ;
files = [
"brevia2_top.v",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------
// Design : Counter verilog top module, Lattice Brevia2
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module brevia2_top (
clear_i,
count_i,
clock_i,
clken_o,
led_o
);
input clear_i, count_i, clock_i;
output clken_o;
output [7:0] led_o;
wire s_clock, s_clear, s_count;
wire [7:0] s_Q;
counter u1(
.clock(s_clock),
.clear(s_clear),
.count(s_count),
.Q(s_Q)
);
assign s_clock = clock_i;
assign clken_o = 1;
assign s_clear = ~clear_i;
assign s_count = ~count_i;
assign led_o[7:0] = ~s_Q[7:0];
endmodule
files = [
"brevia2_top.vhd",
"../brevia2_top.lpf",
]
modules = {
"local" : [ "../../../modules/counter/vhdl" ],
}
----------------------------------------------------------
-- Design : Counter VHDL top module, Lattice Brevia2
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity brevia2_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
clken_o: out std_logic;
led_o: out std_logic_vector(7 downto 0)
);
end brevia2_top;
----------------------------------------------------------
architecture structure of brevia2_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
clken_o <= '1';
s_clear <= not clear_i;
s_count <= not count_i;
led_o <= not s_Q;
end architecture structure;
----------------------------------------------------------------
set module [lindex $quartus(args) 0]
if [string match "quartus_map" $module] {
# Include commands here that are run
# after analysis and synthesis
post_message "Running after analysis & synthesis"
}
if [string match "quartus_fit" $module] {
# Include commands here that are run
# after fitter (Place & Route)
post_message "Running after place & route"
}
if [string match "quartus_asm" $module] {
# Include commands here that are run
# after assembler (Generate programming files)
post_message "Running after timing analysis"
}
if [string match "quartus_tan" $module] {
# Include commands here that are run
# after timing analysis
post_message "Running after timing analysis"
}
post_message "Assigning pinout"
# Load Quartus II Tcl Project package
package require ::quartus::project
project_open -revision demo demo
set_location_assignment PIN_F1 -to clear_i
set_location_assignment PIN_F2 -to count_i
set_location_assignment PIN_B9 -to clock_i
set_location_assignment PIN_N9 -to led_o[3]
set_location_assignment PIN_N12 -to led_o[2]
set_location_assignment PIN_P12 -to led_o[1]
set_location_assignment PIN_P13 -to led_o[0]
# Commit assignments
export_assignments
project_close
files = [
"cyclone3_top.v",
]
modules = {
"local" : [ "../../../modules/counter/verilog" ],
}
//--------------------------------------------------------------------
// Design : Counter verilog top module, Altera CycloneIII Starter Kit
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------------------
module cyclone3_top (
clear_i,
count_i,
clock_i,
led_o
);
input clear_i, count_i, clock_i;
output [3:0] led_o;
wire s_clock,