Bumping documentation to 2.1

parent 3b727474
......@@ -6,8 +6,6 @@
Welcome to hdlmake's documentation!
===================================
.. warning:: The full project documentation is under development. Check this space as new content will be added in the coming days.
.. toctree::
:maxdepth: 2
......@@ -95,6 +93,8 @@ Supported Tools
+--------------------------+-----------+------------+
| Xilinx PlanAhead | Yes | No |
+--------------------------+-----------+------------+
| Xilinx Vivado | Yes | No |
+--------------------------+-----------+------------+
| Altera Quartus | Yes | n.a. |
+--------------------------+-----------+------------+
| Microsemi (Actel) Libero | Yes | n.a. |
......@@ -107,7 +107,7 @@ Supported Tools
+--------------------------+-----------+------------+
| Aldec Active-HDL | n.a. | Yes |
+--------------------------+-----------+------------+
| Icarus Verilog | n.a. | Verilog |
| Icarus Verilog | n.a. | Yes |
+--------------------------+-----------+------------+
| GHDL | n.a. | VHDL |
+--------------------------+-----------+------------+
......@@ -182,7 +182,7 @@ Despite the fact that ``hdlmake`` was originally designed to be used in Linux en
First, install a valid Cygwin environment for your Windows machine. I order to access to the full set of features from ``hdlmake``, you must choose at least the following packages when deploying Cygwin:
- python (choose the most updated 2.7 release)
- python (choose the most up-to-date 2.7 release)
- openssh
- git-svn
- git
......@@ -301,6 +301,8 @@ Each of the modules contains a single testbench file written in the appropriated
While in Verilog the Manifest.py is:
.. code-block:: python
files = [
"counter_tb.v",
]
......@@ -376,7 +378,7 @@ The following common top specific Manifest variables describes the simulation:
- ``action``: indicates that we are going to perform a simulation.
- ``sim_tool``: indicates that modelsim is going to be the simulation we are going to use.
- ``top_module``: indicates the name of the top HDL entity/instance that is going to be simulated.
- ``sim_post_cmd``: indicates a command that can be issued after the simulation process has finnished.
- ``sim_post_cmd``: indicates a command that must be issued after the simulation process has finnished.
Now, if we want to launch the simulation, we must follow the next steps. First, get into the folder containing the top Manifest.py we want to execute and run ``hdlmake`` without arguments. e.g. for VHDL:
......@@ -392,11 +394,11 @@ This generates a simulation Makefile that can be executed by issuing the well kn
user@host:~$ make
user@host:~$ vsim -do ../vsim.do -i counter_tb
But, because we have already defined a post simulation command into the Manifest.py, the generated Makefile allows us to combine the compilation and the test run in a single command:
But, because we have already defined a post simulation command into the Manifest.py, the generated Makefile allows us to combine the compilation and the test run in a single command. In this way, the second command is not required:
.. code-block:: bash
user@host:~$ make sim_post_cmd
user@host:~$ make
If everything goes well, a graphical viewer should appear showing the simulated waveform. Note that every simulation top Manifest.py in the ``sim`` folder includes a tool specific ``sim_post_command``, so all the simulations in this example can be generated by using the same simple command sequence that has been exposed here.
......@@ -471,6 +473,8 @@ Note that we have a different tool associated to each of the different supported
If we focus on the ``spec_v4_ise`` test case, we can see the following contents in the associated folder:
.. code-block:: bash
user@host:~$ tree -d -L 1 counter/syn/spec_v4_ise
counter/syn/spec_v4_ise/
|-- verilog
......
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