Commit de91d33a authored by Javier D. Garcia Lasheras's avatar Javier D. Garcia Lasheras

Merge branch 'adrian_instantiation_sensitiveness' into develop

parents fa7350bc 75957054
......@@ -38,11 +38,16 @@ class SourceFile(DepFile):
assert isinstance(path, basestring)
assert isinstance(module, Module)
self.library = library
if not library:
self.library = "work"
DepFile.__init__(self,
file_path=path,
module=module,
include_paths=module.include_dirs[:])
def __hash__(self):
return hash(self.path + self.library)
class VHDLFile(SourceFile):
def __init__(self, path, module, library=None, vcom_opt=None):
......@@ -64,8 +69,6 @@ class VHDLFile(SourceFile):
class VerilogFile(SourceFile):
def __init__(self, path, module, library=None, vlog_opt=None, include_dirs=None):
if not library:
library = "work"
SourceFile.__init__(self, path=path, module=module, library=library)
if not vlog_opt:
self.vlog_opt = ""
......
......@@ -76,7 +76,7 @@ VLOG_FLAGS := -quiet -modelsimini modelsim.ini """ + self.__get_rid_of_vsim_incd
make_preambule_p1 = make_preambule_p1.format(os.path.join("$(HDLMAKE_MODELSIM_PATH)", ".."))
make_preambule_p2 = string.Template("""## rules #################################
sim: sim_pre_cmd modelsim.ini $$(LIB_IND) $$(VERILOG_OBJ) $$(VHDL_OBJ)
$$(VERILOG_OBJ): $$(VHDL_OBJ)
$$(VERILOG_OBJ) : modelsim.ini
$$(VHDL_OBJ): $$(LIB_IND) modelsim.ini
sim_pre_cmd:
......
......@@ -3,6 +3,7 @@
#
# Copyright (c) 2013 CERN
# Author: Tomasz Wlostowski (tomasz.wlostowski@cern.ch)
# Adrian Fiergolski (Adrian.Fiergolski@cern.ch)
#
# This file is part of Hdlmake.
#
......@@ -100,64 +101,79 @@ class VHDLParser(DepParser):
else:
prev_is_gap = False
buf2 += c.lower()
if c == ";":
if ( (c == ";") or (buf2[-8:] == "generate") or (buf2[-5:] == "begin")) :
lines.append(buf2)
buf2 = ""
else:
prev_is_gap = False
import re
def use() :
if ( g.group(1).lower() == "work" ) : #work is the current library in VHDL
logging.debug("use package %s.%s" % (dep_file.library, g.group(2)) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(2)) , DepRelation.USE, DepRelation.PACKAGE))
else :
logging.debug("use package %s.%s" % (g.group(1), g.group(2)) )
dep_file.add_relation(DepRelation("%s.%s" % (g.group(1), g.group(2)), DepRelation.USE, DepRelation.PACKAGE))
def entity() :
logging.debug("found entity %s.%s" % ( dep_file.library, g.group(1) ) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.ENTITY))
def package() :
logging.debug("found package %s.%s" % (dep_file.library, g.group(1) ))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
def arch_begin() :
arch_name = g.group(1)
within_architecture = True
def arch_end() :
within_architecture = False
def instance() :
for lib in libraries :
logging.debug("-> instantiates %s.%s as %s" % (lib, g.group(2), g.group(1)) )
dep_file.add_relation(DepRelation("%s.%s" % (lib, g.group(2)),
DepRelation.USE,
DepRelation.ENTITY))
def instance_from_library() :
if ( g.group(2).lower() == "work" ) : #work is the current library in VHDL
logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, g.group(3), g.group(1)) )
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(3)),
DepRelation.USE,
DepRelation.ENTITY))
else :
logging.debug("-> instantiates %s.%s as %s" % (g.group(2), g.group(3), g.group(1)) )
dep_file.add_relation(DepRelation("%s.%s" % (g.group(2), g.group(3)),
DepRelation.USE,
DepRelation.ENTITY))
def library() :
logging.debug("use library %s" % g.group(1) )
libraries.add(g.group(1))
patterns = {
"use": "^ *use +(\w+) *\. *(\w+) *\. *\w+ *;",
"entity": "^ *entity +(\w+) +is +(port|generic)",
"package": "^ *package +(\w+) +is",
"arch_begin": "^ *architecture +(\w+) +of +(\w+) +is +",
"arch_end": "^ *end +(\w+) +;",
"instance": "^ *(\w+) *\: *(\w+) *(port|generic) *map"
use: "^ *use +(\w+) *\. *(\w+) *\. *\w+ *;",
entity: "^ *entity +(\w+) +is +(?:port|generic|end)",
package: "^ *package +(\w+) +is",
arch_begin: "^ *architecture +(\w+) +of +(\w+) +is +",
arch_end: "^ *end +(\w+) +;",
instance: "^ *(\w+) *\: *(\w+) *(?:port +map|generic +map| *;)",
instance_from_library: "^ *(\w+) *\: *entity *(\w+) *\. *(\w+) *(?:port +map|generic +map| *;)",
library: "^ *library *(\w+) *;"
}
compiled_patterns = map(lambda p: (p, re.compile(patterns[p])), patterns)
within_architecture = False
libraries = set([dep_file.library])
for l in lines:
matches = filter(lambda (k, v): v is not None, map(lambda (k, v): (k, re.match(v, l)), compiled_patterns))
matches = filter(lambda (k, v): v is not None, map(lambda (k, v): (k, re.match(v, l.lower())), compiled_patterns))
# logging.debug("%s" % l )
if(not len(matches)):
continue
what, g = matches[0]
if(what == "use"):
dep_file.add_relation(DepRelation(g.group(1)+"."+g.group(2), DepRelation.USE, DepRelation.PACKAGE))
if(what == "package"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
elif(what == "entity"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.ENTITY))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.ENTITY))
elif(what == "package"):
dep_file.add_relation(DepRelation(g.group(1),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
dep_file.add_relation(DepRelation("%s.%s" % (dep_file.library, g.group(1)),
DepRelation.PROVIDE,
DepRelation.PACKAGE))
elif(what == "arch_begin"):
arch_name = g.group(1)
within_architecture = True
elif(what == "arch_end" and within_architecture and g.group(1) == arch_name):
within_architecture = False
elif(what == "instance" and within_architecture):
dep_file.add_relation(DepRelation(g.group(2),
DepRelation.USE,
DepRelation.ENTITY))
dep_file.is_parsed = True
\ No newline at end of file
what()
dep_file.is_parsed = True
......@@ -34,19 +34,11 @@ from srcfile import SourceFileFactory
class VerilogPreprocessor(object):
# Reserved verilog preprocessor keywords. The list is certainly not full
# Reserved verilog preprocessor keywords. The list is certainly not full
vpp_keywords = ["define", "line", "include", "elsif", "ifdef", "endif", "else", "undef", "timescale"]
# List of `include search paths
vpp_searchdir = ["."]
# List of macro definitions
vpp_macros = []
# Dictionary of files sub-included by each file parsed
vpp_filedeps = {}
# Verilog `define class
# Verilog `define class
class VL_Define(object):
def __init__(self, name, args, expansion):
self.name = name
......@@ -73,6 +65,13 @@ class VerilogPreprocessor(object):
def __init__(self):
self.vpp_stack = self.VL_Stack()
self.vlog_file = None
# List of `include search paths
self.vpp_searchdir = ["."]
# List of macro definitions
self.vpp_macros = []
# Dictionary of files sub-included by each file parsed
self.vpp_filedeps = {}
def _find_macro(self, name):
for m in self.vpp_macros:
......@@ -137,7 +136,7 @@ class VerilogPreprocessor(object):
self.vpp_macros.append(mdef)
return mdef
def _preprocess_file(self, file_content, file_name):
def _preprocess_file(self, file_content, file_name, library):
exps = {"include": re.compile("^\s*`include\s+\"(.+)\""),
"define": re.compile("^\s*`define\s+(\w+)(?:\(([\w\s,]*)\))?(.*)"),
"ifdef_elsif": re.compile("^\s*`(ifdef|ifndef|elsif)\s+(\w+)\s*$"),
......@@ -145,11 +144,11 @@ class VerilogPreprocessor(object):
vl_macro_expand = re.compile("`(\w+)(?:\(([\w\s,]*)\))?")
# init dependencies
self.vpp_filedeps[file_name] = []
self.vpp_filedeps[file_name + library] = []
cur_iter = 0
logging.debug("preprocess file %s (of length %d)" % (file_name, len(file_content)))
logging.debug("preprocess file %s (of length %d) in library %s" % (file_name, len(file_content), library))
# print("BUF '%s'" %buf)
buf = self._remove_comment(file_content)
while True:
......@@ -188,12 +187,12 @@ class VerilogPreprocessor(object):
if matches["include"]:
included_file_path = self._search_include(last.group(1), os.path.dirname(file_name))
logging.debug("File being parsed %s includes %s" % (file_name, included_file_path))
logging.debug("File being parsed %s (library %s) includes %s" % (file_name, library, included_file_path))
line = self._preprocess_file(file_content=open(included_file_path, "r").read(),
file_name=included_file_path)
self.vpp_filedeps[file_name].append(included_file_path)
file_name=included_file_path, library=library)
self.vpp_filedeps[file_name + library].append(included_file_path)
# add the whole include chain to the dependencies of the currently parsed file
self.vpp_filedeps[file_name].extend(self.vpp_filedeps[included_file_path])
self.vpp_filedeps[file_name + library].extend(self.vpp_filedeps[included_file_path + library])
new_buf += line + '\n'
n_expansions += 1
continue
......@@ -235,7 +234,7 @@ class VerilogPreprocessor(object):
self.vlog_file = vlog_file
file_path = vlog_file.file_path
buf = open(file_path, "r").read()
return self._preprocess_file(file_content=buf, file_name=file_path)
return self._preprocess_file(file_content=buf, file_name=file_path, library = vlog_file.library)
def _find_first(self, f, l):
x = filter(f, l)
......@@ -535,6 +534,7 @@ class VerilogParser(DepParser):
return buf2
def parse(self, dep_file):
i = 0;
if dep_file.is_parsed:
return
logging.info("Parsing %s" % dep_file.path)
......@@ -544,7 +544,7 @@ class VerilogParser(DepParser):
#add includes as dependencies
try:
includes = self.preprocessor.vpp_filedeps[dep_file.path]
includes = self.preprocessor.vpp_filedeps[dep_file.path + dep_file.library]
for f in includes:
dep_file.depends_on.add(SourceFileFactory().new(path=f, module=dep_file.module))
logging.debug( "%s has %d includes." % (str(dep_file), len(includes)))
......@@ -561,15 +561,15 @@ class VerilogParser(DepParser):
#and HdlMake will anyway create dependency marking my_other_module as requested package
import_pattern = re.compile("(\w+) *::(\w+|\\*)")
def do_imports(s):
logging.debug("file %s imports/uses %s package" %( dep_file.path , s.group(1) ) )
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.PACKAGE))
logging.debug("file %s imports/uses %s.%s package" %( dep_file.path , dep_file.library, s.group(1) ) )
dep_file.add_relation( DepRelation( "%s.%s" % (dep_file.library, s.group(1)) , DepRelation.USE, DepRelation.PACKAGE))
re.subn(import_pattern, do_imports, buf)
#packages
m_inside_package = re.compile("package\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)endpackage", re.DOTALL | re.MULTILINE)
def do_package(s):
logging.debug("found pacakge %s" %s.group(1))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.PACKAGE))
logging.debug("found pacakge %s.%s" %(dep_file.library, s.group(1)) )
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.PACKAGE))
re.subn(m_inside_package, do_package, buf)
#modules and instatniations
......@@ -577,15 +577,15 @@ class VerilogParser(DepParser):
m_instantiation = re.compile("(?:\A|\\s*)\s*(\w+)\s+(?:#\s*\(.*?\)\s*)?(\w+)\s*\(.*?\)\s*", re.DOTALL | re.MULTILINE)
def do_module(s):
logging.debug("found module %s" %s.group(1))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.PROVIDE, DepRelation.ENTITY))
logging.debug("found module %s.%s" % (dep_file.library, s.group(1) ))
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.PROVIDE, DepRelation.ENTITY))
def do_inst(s):
mod_name = s.group(1)
if(mod_name in self.reserved_words):
return
logging.debug("-> instantiates %s as %s" % (s.group(1), s.group(2) ))
dep_file.add_relation(DepRelation(s.group(1), DepRelation.USE, DepRelation.ENTITY))
logging.debug("-> instantiates %s.%s as %s" % (dep_file.library, s.group(1), s.group(2) ))
dep_file.add_relation(DepRelation( "%s.%s" % (dep_file.library, s.group(1)), DepRelation.USE, DepRelation.ENTITY))
re.subn(m_instantiation, do_inst, s.group(2))
re.subn(m_inside_module, do_module, buf)
......
include_dirs = "./include"
files = ["include/includeModule.sv",
files = ["include/includeModuleSV.sv",
"include/includeModuleVHDL.vhdl",
"include/includeModuleAVHDL.vhdl",
"include/includeModuleBVHDL.vhdl",
"RTL_SVPackage.sv",
"RTLTopModuleSV.sv",
"RTLTopModuleVerilogSimulationModel.vo",
......
......@@ -14,7 +14,7 @@ module RTLTopModuleSV;
initial
l1a <= RTL_SVPackage::CONST;
includeModule incl();
includeModuleSV incl();
ipcore ip();
endmodule // RTLTopModuleSV
-------------------------------------------------------------------------------
-- Title : RTLTopModuleVHDL
-- Project :
-- Title : RTLTopModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : RTLTopModuleVHDL.vhdl
-- Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch>
-- Company : CERN
-- Created : 2014-09-26
-- Last update: 2014-09-26
-- Platform :
-- Standard : VHDL'2008
-- File : RTLTopModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version 3 of the License, or any later version.
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-09-26 1.0 afiergol Created
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity RTLTopModuleVHDL is
end entity RTLTopModuleVHDL;
architecture Behavioral of RTLTopModuleVHDL is
component includeModuleVHDL is
end component;
signal probe : STD_LOGIC;
begin -- architecture Behavioral
begin -- architectureecture Behavioral
probe <= '1';
include_module : includeModuleVHDL;
a : entity work.includeModuleAVHDL;
GEN : for i in 0 to 3 generate
B : entity work.includeModuleBVHDL;
end generate;
end architecture Behavioral;
-------------------------------------------------------------------------------
-- Title : includeModuleAVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleAVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleAVHDL is
end entity includeModuleAVHDL;
architecture Behavioral of includeModuleAVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
-------------------------------------------------------------------------------
-- Title : includeModuleBVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleBVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleBVHDL is
end entity includeModuleBVHDL;
architecture Behavioral of includeModuleBVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
// -*- Mode: Verilog -*-
// Filename : includeModule.sv
// Filename : includeModuleSV.sv
// Description : Included submodule
// Author : Adrian Fiergolski
// Created On : Thu Sep 18 10:51:41 2014
......@@ -8,7 +8,7 @@
// Update Count : 0
// Status : Unknown, Use with caution!
module includeModule;
module includeModuleSV;
endmodule // includeModule
endmodule // includeModuleSV
-------------------------------------------------------------------------------
-- Title : includeModuleVHDL Project :
-------------------------------------------------------------------------------
-- File : includeModuleVHDL.vhdl Author : Adrian Fiergolski <Adrian.Fiergolski@cern.ch> Company : CERN Created : 2014-09-26 Last update: 2014-09-26 Platform : Standard : VHDL'2008
-------------------------------------------------------------------------------
-- Description: The module to test HDLMake
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
--
-- This file is part of .
--
-- is free firmware: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with . If not, see http://www.gnu.org/licenses/.
-------------------------------------------------------------------------------
-- Revisions : Date Version Author Description 2014-09-26 1.0 afiergol Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity includeModuleVHDL is
end entity includeModuleVHDL;
architecture Behavioral of includeModuleVHDL is
signal probe : STD_LOGIC;
begin -- architecture Behavioral
end architecture Behavioral;
......@@ -11,29 +11,35 @@ MODELSIM_INI_PATH := /opt/questa_sv_afv_10.3c_1/questasim//bin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC := ../../rtl/RTL_SVPackage.sv \
../../rtl/include/includeModule.sv \
../../ipcores/ipcore/ipcore.sv \
../../rtl/RTLTopModuleSV.sv \
VERILOG_SRC := src/genericTest.sv \
../../rtl/RTLTopModuleVerilogSimulationModel.vo \
src/genericTest.sv \
../../rtl/RTL_SVPackage.sv \
../../rtl/RTLTopModuleSV.sv \
../../rtl/include/includeModuleSV.sv \
../../ipcores/ipcore/ipcore.sv \
VERILOG_OBJ := work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
VERILOG_OBJ := work/genericTest/.genericTest_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
work/genericTest/.genericTest_sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/includeModuleSV/.includeModuleSV_sv \
work/ipcore/.ipcore_sv \
VHDL_SRC := ../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_SRC := ../../rtl/include/includeModuleVHDL.vhdl \
../../rtl/include/includeModuleAVHDL.vhdl \
../../rtl/include/includeModuleBVHDL.vhdl \
../../rtl/RTLTopModuleVHDL.vhdl \
VHDL_OBJ := work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
VHDL_OBJ := work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl \
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl \
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: sim_pre_cmd modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VERILOG_OBJ) : modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
sim_pre_cmd:
......@@ -45,55 +51,72 @@ sim_post_cmd: sim
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
clean:
rm -rf ./modelsim.ini $(LIBS)
rm -rf ./modelsim.ini $(LIBS) transcript *.vcd *.wlf
.PHONY: clean sim_pre_cmd sim_post_cmd
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
work/genericTest/.genericTest_sv: src/genericTest.sv \
../environment/env.sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
../environment/Env_pkg.sv \
src/FullTest_pkg.sv \
../environment/top.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
../sequences/sequence.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
@mkdir -p $(dir $@) && touch $@
work/includeModule/.includeModule_sv: ../../rtl/include/includeModule.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
work/RTL_SVPackage/.RTL_SVPackage_sv: ../../rtl/RTL_SVPackage.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleSV/.RTLTopModuleSV_sv: ../../rtl/RTLTopModuleSV.sv \
work/RTL_SVPackage/.RTL_SVPackage_sv \
work/includeModule/.includeModule_sv \
work/ipcore/.ipcore_sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo: ../../rtl/RTLTopModuleVerilogSimulationModel.vo
vlog -work work $(VLOG_FLAGS) +incdir+../../rtl/include+../../rtl $<
work/includeModuleSV/.includeModuleSV_sv: ../../rtl/include/includeModuleSV.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../rtl/include+../../rtl/include $<
@mkdir -p $(dir $@) && touch $@
work/genericTest/.genericTest_sv: src/genericTest.sv \
../sequences/sequence.sv \
../environment/Env_pkg.sv \
../environment/env.sv \
work/RTLTopModuleSV/.RTLTopModuleSV_sv \
work/RTLTopModuleVerilogSimulationModel/.RTLTopModuleVerilogSimulationModel_vo \
../environment/top.sv \
src/FullTest_pkg.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../environment+../sequences+src +incdir+../../mvc//questa_mvc_src/sv+../../mvc/questa_mvc_src/sv/mvc_base+../../mvc/include+../../uvm-1.1d/src $<
work/ipcore/.ipcore_sv: ../../ipcores/ipcore/ipcore.sv \
../../ipcores/ipcore/include/ipcoreInclude.sv
vlog -work work $(VLOG_FLAGS) -sv +incdir+../../ipcores/ipcore/include+../../ipcores/ipcore $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl
work/includeModuleVHDL/.includeModuleVHDL_vhdl: ../../rtl/include/includeModuleVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl: ../../rtl/include/includeModuleAVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl: ../../rtl/include/includeModuleBVHDL.vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/RTLTopModuleVHDL/.RTLTopModuleVHDL_vhdl: ../../rtl/RTLTopModuleVHDL.vhdl \
work/includeModuleVHDL/.includeModuleVHDL_vhdl \
work/includeModuleAVHDL/.includeModuleAVHDL_vhdl \
work/includeModuleBVHDL/.includeModuleBVHDL_vhdl
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
......
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