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Commit ea646dfd authored by Pawel Szostek's avatar Pawel Szostek Committed by Javier D. Garcia Lasheras

tune vlog parser to include dependency chains

parent e26f48c3
......@@ -114,11 +114,11 @@ class VerilogPreprocessor(object):
if parent_dir is not None:
possible_file = os.path.join(parent_dir, filename)
if(os.path.isfile(possible_file)):
return possible_file
return os.path.abspath(possible_file)
for searchdir in self.vpp_searchdir:
probable_file = os.path.join(searchdir, filename)
if(os.path.isfile(probable_file)):
return probable_file
return os.path.abspath(probable_file)
logging.error("Can't find %s for %s in any of the include directories: %s"
% (filename, self.vlog_file.file_path, ', '.join(self.vpp_searchdir)))
sys.exit("\nExiting")
......@@ -143,6 +143,8 @@ class VerilogPreprocessor(object):
"endif_else": re.compile("^\s*`(endif|else)\s*$")}
vl_macro_expand = re.compile("`(\w+)(?:\(([\w\s,]*)\))?")
# init dependencies
self.vpp_filedeps[file_name] = []
cur_iter = 0
......@@ -158,10 +160,10 @@ class VerilogPreprocessor(object):
for line in self._degapize(buf):
matches = {}
last = None
for k in exps.iterkeys():
matches[k] = re.match(exps[k], line)
if(matches[k]):
last = matches[k]
for statement, stmt_regex in exps.iteritems():
matches[statement] = re.match(stmt_regex, line)
if(matches[statement]):
last = matches[statement]
if matches["ifdef_elsif"]:
cond_true = self._find_macro(last.group(2)) is not None
......@@ -184,14 +186,15 @@ class VerilogPreprocessor(object):
continue
if matches["include"]:
path = self._search_include(last.group(1), os.path.dirname(file_name))
logging.debug("Parsed cur. %s file includes %s" % (file_name, path))
line = self._preprocess_file(file_content=open(path, "r").read(),
file_name=path)
# print("IncBuf '%s'" % parsed)
if file_name not in self.vpp_filedeps.iterkeys():
self.vpp_filedeps[file_name] = [path]
included_file_path = self._search_include(last.group(1), os.path.dirname(file_name))
logging.debug("File being parsed %s includes %s" % (file_name, included_file_path))
line = self._preprocess_file(file_content=open(included_file_path, "r").read(),
file_name=included_file_path)
self.vpp_filedeps[file_name].append(included_file_path)
# add the whole include chain to the dependencies of the currently parsed file
self.vpp_filedeps[file_name].extend(self.vpp_filedeps[included_file_path])
new_buf += line + '\n'
n_expansions += 1
continue
elif matches["define"]:
......@@ -213,8 +216,8 @@ class VerilogPreprocessor(object):
new_buf += repl_line + '\n'
# if there was any expansion, then keep on iterating
if repl_line != line:
n_expansions += 1
buf = new_buf
n_expansions += 1
buf = new_buf
if n_expansions == 0:
return new_buf
......@@ -539,8 +542,13 @@ class VerilogParser(DepParser):
self.preprocessed = buf[:]
#add includes as dependencies
for f in self.preprocessor.vpp_filedeps:
dep_file.add_relation(DepRelation(f, DepRelation.USE, DepRelation.INCLUDE))
try:
includes = self.preprocessor.vpp_filedeps[dep_file.path]
for f in includes:
dep_file.depends_on.add(SourceFileFactory().new(path=f, module=dep_file.module))
logging.debug( "%s has %d includes." % (str(dep_file), len(includes)))
except KeyError:
logging.debug(str(dep_file) + " has no includes.")
m_inside_module = re.compile("(?:module|interface)\s+(\w+)\s*(?:\(.*?\))?\s*(.+?)(?:endmodule|endinterface)", re.DOTALL | re.MULTILINE)
m_instantiation = re.compile("(?:\A|\\s*)\s*(\w+)\s+(?:#\s*\(.*?\)\s*)?(\w+)\s*\(.*?\)\s*", re.DOTALL | re.MULTILINE)
......@@ -558,5 +566,5 @@ class VerilogParser(DepParser):
re.subn(m_instantiation, do_inst, s.group(2))
re.subn(m_inside_module, do_module, buf)
dep_file.add_relation(DepRelation(os.path.basename(dep_file.filename), DepRelation.PROVIDE, DepRelation.INCLUDE))
dep_file.add_relation(DepRelation(dep_file.path, DepRelation.PROVIDE, DepRelation.INCLUDE))
dep_file.is_parsed = True
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