Commit fa0d59ac authored by Javier D. Garcia Lasheras's avatar Javier D. Garcia Lasheras

Merge branch 'iverilog-vhdl-counter-test' into develop

parents 6d4d3661 c3aecb01
......@@ -70,7 +70,8 @@ class ToolControls(MakefileWriter):
makefile_tmplt_1 = string.Template("""TOP_MODULE := ${top_module}
run.command \
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
action = "simulation"
sim_tool = "iverilog"
top_module = "counter_tb"
sim_pre_cmd ="echo IMPORTANT, IVerilog always needs a Verilog testbench, no matter if the DUT is written in VHDL!"
sim_post_cmd = "vvp counter_tb.vvp; gtkwave counter_tb.vcd"
files = [
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