First version of the Getting Started with the SPEC code

parent 393889c6
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
FEBRUARY 2014
DATE 20140224
THIS IS JUST A SANDBOX -- ACTUAL WORK IS UNDER DEVELOPMENT!!
THE REPOSITORY IS BEING CONTINUOUSLY CLEANED AND RE-INITIALIZED AS THE FIRST BETA VERSION IS NOT RELEASED YET
PLEASE, DON'T TRUST THIS CODE ;-)
JAVI
First version of the Getting Started with the SPEC project is released.
*.*\#
\#*
.\#*
*.*~
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
*.h
*.o
*.bin
*.elf
Makefile
general-cores @ fc55d71b
Subproject commit fc55d71bb81f86c2f4770b3fae8da0b15d096316
gn4124-core @ f26b97a5
Subproject commit f26b97a564b43c8119ef7dd8e156088ab9346390
files = ["fmc_dio_ch5_ttl.vhd", "wb_slave_fmc_dio_ch5_ttl.vhd" ]
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wb_slave_fmc_dio_ch5_ttl.in -f texinfo wb_slave_fmc_dio_ch5_ttl.wb
wbgen2 -D ./doc/wb_slave_fmc_dio_ch5_ttl.html -V wb_slave_fmc_dio_ch5_ttl.vhd -H signals --lang vhdl wb_slave_fmc_dio_ch5_ttl.wb
This diff is collapsed.
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{ddr} @tab
Pin direction register
@item @code{0x4} @tab
REG @tab
@code{psr} @tab
Pin state register
@item @code{0x8} @tab
REG @tab
@code{pdr} @tab
Pin output register
@item @code{0xc} @tab
REG @tab
@code{term} @tab
Pin termination register
@item @code{0x10} @tab
REG @tab
@code{sopr} @tab
Set output pin register
@item @code{0x14} @tab
REG @tab
@code{copr} @tab
Clear output pin register
@item @code{0x20} @tab
REG @tab
@code{leds} @tab
LED signaling interface
@end multitable
@regsection @code{ddr} - Pin direction register
A register defining the direction of the DIO pins.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/W @tab
@code{DDR}
@tab @code{0} @tab
Pin directions
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ddr} @tab Each bit in this register defines the direction of the corresponding pin in the DIO. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT
@end multitable
@regsection @code{psr} - Pin state register
A register containing the current state of the DIO pins.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PSR}
@tab @code{X} @tab
Pin input state
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{psr} @tab Each bit in this register reflects the state of the corresponding pin in the DIO. 1 means the pin is HIGH, 0 means the pin is LOW
@end multitable
@regsection @code{pdr} - Pin output register
A register that allows changing the value of the DIO pins by means of a direct write access
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{PDR}
@tab @code{0} @tab
Pin output value
@end multitable
@regsection @code{term} - Pin termination register
A register defining the use of the 50 Ohm termination
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/W @tab
@code{TERM}
@tab @code{0} @tab
Pin terminations
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{term} @tab Writing '1' activates the termination resistor
@end multitable
@regsection @code{sopr} - Set output pin register
Writing '1' sets the corresponding DIO pin to '1'
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{SOPR}
@tab @code{0} @tab
Set output pin register
@end multitable
@regsection @code{copr} - Clear output pin register
Writing '1' clears the corresponding DIO pin
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{COPR}
@tab @code{0} @tab
Clear output pin register
@end multitable
@regsection @code{leds} - LED signaling interface
Writing '1' activates the corresponding LED
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{BOT}
@tab @code{0} @tab
FMC DIO Bottom LED
@item @code{1}
@tab R/W @tab
@code{TOP}
@tab @code{0} @tab
FMC DIO Top LED
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{bot} @tab Control bit for the bottom LED placed on the FMC DIO front panel
@item @code{top} @tab Control bit for the top LED placed on the FMC DIO front panel
@end multitable
-------------------------------------------------------------------------------
-- Title : FMC DIO Ch5 TTL
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : fmc_dio_ch5_ttl.vhd
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Very simple core for handling the fmc-dio-ch5ttl module.
-- It allows a direct access to the FMC pins that control the basic functions.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity fmc_dio_ch5_ttl is
port (
-- Whishbone Interface
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- FMC DIO 5ch TTL port
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_led_bot_o : out std_logic;
dio_led_top_o : out std_logic
);
end fmc_dio_ch5_ttl;
architecture rtl of fmc_dio_ch5_ttl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component wb_slave_fmc_dio_5ch_ttl is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fmc_dio_async_clk_i : in std_logic;
-- Port for std_logic_vector field: 'Pin directions' in reg: 'Pin direction register'
fmc_dio_ddr_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Pin input state' in reg: 'Pin input state register'
fmc_dio_psr_i : in std_logic_vector(4 downto 0);
-- Ports for PASS_THROUGH field: 'Port output value' in reg: 'Port output register'
fmc_dio_pdr_o : out std_logic_vector(4 downto 0);
fmc_dio_pdr_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pin terminations' in reg: 'Pin termination register'
fmc_dio_term_o : out std_logic_vector(4 downto 0);
-- Ports for PASS_THROUGH field: 'Set output pin register' in reg: 'Set output pin register'
fmc_dio_sopr_o : out std_logic_vector(4 downto 0);
fmc_dio_sopr_wr_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Clear output pin register' in reg: 'Clear output pin register'
fmc_dio_copr_o : out std_logic_vector(4 downto 0);
fmc_dio_copr_wr_o : out std_logic;
-- Port for BIT field: 'FMC DIO Bottom LED' in reg: 'LED signaling interface'
fmc_dio_leds_bot_o : out std_logic;
-- Port for BIT field: 'FMC DIO Top LED' in reg: 'LED signaling interface'
fmc_dio_leds_top_o : out std_logic
);
end component; -- wb_slave_fmc_dio_5ch_ttl
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal dio_bus_ddr_o : std_logic_vector(4 downto 0);
signal dio_bus_psr_i : std_logic_vector(4 downto 0);
signal dio_bus_pdr_o : std_logic_vector(4 downto 0);
signal dio_bus_pdr_wr_o : std_logic;
signal dio_bus_term_o : std_logic_vector(4 downto 0);
signal dio_bus_sopr_o : std_logic_vector(4 downto 0);
signal dio_bus_sopr_wr_o : std_logic;
signal dio_bus_copr_o : std_logic_vector(4 downto 0);
signal dio_bus_copr_wr_o : std_logic;
-- regsiter containing current output state
signal dio_reg : std_logic_vector(4 downto 0);
-- registers for synchronization of input pins
signal dio_pins_sync1 : std_logic_vector(4 downto 0);
signal dio_pins_sync0 : std_logic_vector(4 downto 0);
begin
gen_dio_iobufs : for i in 0 to 4 generate
-- Digital Input Differential Signaling Buffers
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i)
);
-- Digital Output Differential Signaling Buffers
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
-- Clock Input Differential Signaling Buffer
U_input_buffer : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_clk,
I => dio_clk_p_i,
IB => dio_clk_n_i
);
wb_dio_port : wb_slave_fmc_dio_5ch_ttl
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
fmc_dio_async_clk_i => clk_sys_i,
fmc_dio_ddr_o => dio_bus_ddr_o,
fmc_dio_psr_i => dio_bus_psr_i,
fmc_dio_pdr_o => dio_bus_pdr_o,
fmc_dio_pdr_wr_o => dio_bus_pdr_wr_o,
fmc_dio_term_o => dio_bus_term_o,
fmc_dio_sopr_o => dio_bus_sopr_o,
fmc_dio_sopr_wr_o => dio_bus_sopr_wr_o,
fmc_dio_copr_o => dio_bus_copr_o,
fmc_dio_copr_wr_o => dio_bus_copr_wr_o,
fmc_dio_leds_bot_o => dio_led_bot_o,
fmc_dio_leds_top_o => dio_led_top_o
);
-- FMC DIO REGISTERS HANDLING
process (clk_sys_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
dio_reg <= (others => '0');
elsif rising_edge(clk_sys_i) then
if(dio_bus_pdr_wr_o = '1') then -- write operation to "PDR" register
-- set the new values of GPIO outputs
dio_reg <= dio_bus_pdr_o;
end if;
if(dio_bus_sopr_wr_o = '1') then -- write to "SOPR" reg - set ones
for i in 0 to 4 loop
if(dio_bus_sopr_o(i) = '1') then
dio_reg(i) <= '1';
end if;
end loop;
end if;
if(dio_bus_copr_wr_o = '1') then -- write to "COPR" reg - set zeros
for i in 0 to 4 loop
if(dio_bus_copr_o(i) = '1') then
dio_reg(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-- synchronizing process for input pins
synchronize_input_pins : process (clk_sys_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
dio_pins_sync0 <= (others => '0');
dio_pins_sync1 <= (others => '0');
elsif rising_edge(clk_sys_i) then
dio_pins_sync0 <= dio_in;
dio_pins_sync1 <= dio_pins_sync0;
end if;
end process;
-- generate the pin interface for I/O channels
gen_pin_interface : for i in 0 to 4 generate
dio_bus_psr_i(i) <= dio_pins_sync1(i) when dio_bus_ddr_o(i) = '0' else dio_reg(i);
dio_out(i) <= dio_reg(i);
dio_oe_n_o(i) <= not dio_bus_ddr_o(i);
dio_term_en_o(i) <= dio_bus_term_o(i);
end generate gen_pin_interface;
end rtl;
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-- -*- Mode: LUA; tab-width: 4 -*-
-------------------------------------------------------------------------------
-- Title : WB Slave FMC DIO TTL
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : wb_slave_fmc_dio_ch5_ttl.wb
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : wb (Wishbone Generator)
-------------------------------------------------------------------------------
-- Description:
-- Wishbone generator file used in the SPEC getting started project.
-- It contains a slave description for controlling the basic functions
-- of the fmc-dio-ch5ttl module.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
peripheral {
name = "FMC DIO 5ch TTL Port";
description = "A Wishbone interface for the FMC DIO 5ch TTL";
hdl_entity = "wb_slave_fmc_dio_5ch_ttl";
prefix = "fmc_dio";
reg {
name = "Pin direction register";
description = "A register defining the direction of the DIO pins.";
prefix = "ddr";
field {
name = "Pin directions";
description = "Each bit in this register defines the direction of the corresponding pin in the DIO. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT";
type = SLV;
size = 5;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin state register";
description = "A register containing the current state of the DIO pins.";
prefix = "psr";
field {
name = "Pin input state";
description = "Each bit in this register reflects the state of the corresponding pin in the DIO. 1 means the pin is HIGH, 0 means the pin is LOW";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin output register";
description = "A register that allows changing the value of the DIO pins by means of a direct write access";
prefix = "pdr";
field {
name = "Pin output value";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin termination register";
description = "A register defining the use of the 50 Ohm termination";
prefix = "term";
field {
name = "Pin terminations";
description = "Writing '1' activates the termination resistor";
type = SLV;
size = 5;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Set output pin register";
description = "Writing '1' sets the corresponding DIO pin to '1'";
prefix = "sopr";
align = 4;
field {
name = "Set output pin register";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Clear output pin register";
description = "Writing '1' clears the corresponding DIO pin";
prefix = "copr";
field {
name = "Clear output pin register";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "LED signaling interface";
description = "Writing '1' activates the corresponding LED";
prefix = "leds";
align = 4;
field {
name = "FMC DIO Bottom LED";
description = "Control bit for the bottom LED placed on the FMC DIO front panel";
prefix = "bot";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
field {
name = "FMC DIO Top LED";
description = "Control bit for the top LED placed on the FMC DIO front panel";
prefix = "top";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
};
files = ["reset_generator.vhd"]
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_generator is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_generator;
architecture behavioral of reset_generator is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
files = ["spec_user_interface.vhd"]
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/spec_user_interface.in -f texinfo spec_user_interface.wb
wbgen2 -D ./doc/spec_user_interface.html -V spec_user_interface.vhd -H signals --lang vhdl spec_user_interface.wb
This diff is collapsed.
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{ctrl} @tab
Control register
@item @code{0x4} @tab
REG @tab
@code{aux} @tab
Auxiliar interface
@end multitable
@regsection @code{ctrl} - Control register
A register containing basic SPEC controls
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{VER}
@tab @code{X} @tab
PCB Version
@item @code{4}
@tab R/W @tab
@code{LED_GREEN}
@tab @code{0} @tab
Front panel green LED
@item @code{5}
@tab R/W @tab
@code{LED_RED}
@tab @code{0} @tab
Front panel red LED
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ver} @tab This field accesses to the hard-wired 4 bits that indicate the PCB version
@item @code{led_green} @tab Control bit for the green LED placed on the SPEC front panel
@item @code{led_red} @tab Control bit for the red LED placed on the SPEC front panel
@end multitable
@regsection @code{aux} - Auxiliar interface
A register mapping the SPEC internal auxiliar interface
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{BUTTON1}
@tab @code{X} @tab
User Push-button 1
@item @code{1}
@tab R/O @tab
@code{BUTTON2}
@tab @code{X} @tab
User Push-button 2
@item @code{5...2}
@tab R/W @tab
@code{LEDS}
@tab @code{0} @tab
User Leds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{button1} @tab Status bit for the internal push-button 1
@item @code{button2} @tab Status bit for the internal push-button 2
@item @code{leds} @tab Control field for the 4 internal auxiliar LEDs
@end multitable
This diff is collapsed.
-- -*- Mode: LUA; tab-width: 4 -*-
-------------------------------------------------------------------------------
-- Title : SPEC User Interface
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : spec_user_interface.wb
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : wb (Wishbone Generator)